1. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to the memory unit arrays storing groups of logic signals. The memory unit arrays are typically implemented using transistor-transistor logic (TTL). Thus, the processing of logic signal groups is substantially slower than the processing in the remainder of the data processing system. In particular, while it would be desirable to address a different memory unit array on each system clock cycle, the address for any logic signal group must be applied to a memory unit array for a substantially longer period than a single system clock cycle.
2. Description of the Related Art
Referring to FIG. 1, a typical data processing system is shown. The illustrated data processing system includes central processing units 10 and 11, input/output units 13 and 14, a main memory unit 15 and a system bus 19 coupling together the central processing, input/output, and main memory units of the data processing system. The central processing unit 10 or 11 processes groups of logic signals according to software and/or firmware instructions. The logic signal groups to be processed, as well as a majority of the programs to be executed, are typically stored in the main memory unit 15. A console unit 12 can be coupled to the central processing units and includes apparatus and stored instructions to initialize the system. The console unit 12 can act as a terminal during the operation of the data processing system. The input/output units provide an interface to the remainder of the data processing system components such as terminal units, mass storage units, communication units, and any other units to be coupled to the data processing system. The detailed function of the units coupled to the system bus 19 is less important to an understanding of the present invention than the fact that these units operate autonomously and communicate with the remainder of the data processing system units or subsystems by means of the system bus.
Referring next to FIG. 2, a block diagram of a typical main memory unit 15 found in the related art is shown. The main memory unit 15 includes a memory interface unit 21 that exchanges signals with the system bus 19. The memory interface unit is coupled to a memory unit bus 22 and the memory unit bus 22 has at least one memory array unit 23 coupled thereto. The memory array units 23 each comprise a plurality of logic signal storage elements organized in groups so that each group of storage elements can be accessed by a unique logic signal group address. The memory interface unit 21 includes the apparatus for controlling the exchange of logic signal groups, identified by logic signal group addresses, between the memory array units 23 and the system bus 19. The memory interface unit 21 includes apparatus for identifying activity on the system bus 19 directed to the memory unit 15, as well as apparatus for returning logic signal groups to the subsystems for the data processing units which had requested specific signal groups from main memory. Buffering of the logic signal groups, error correction and generation of control signals are also typically performed in the memory interface unit 21.
The foregoing conventional main memory architecture limits the amount of activity that can be performed in the main memory unit 15. Specifically, because all the activity must be performed under the control of a memory interface unit 21 control unit, only a single activity may be performed at a time. A need has therefore arisen for apparatus and methods of operation for a main memory unit that can permit a multiplicity of simultaneous operations involving that main memory unit. This requirement is particularly stringent in the computer systems referred to as "write through" data processing systems in which a logic signal group from the data processing system is immediately stored or written into the main memory unit. The memory activity resulting from write through data processing system can result in performance deterioration unless the main memory unit can be modified in a manner to accommodate the increased activity.